This invention generally relates to photolithographic patterning of semiconductor features and more particularly to an improved method for reworking a damascene photolithographic patterning step.
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been the stringent requirements placed on photolithographic processes as line width and step heights have decreased for device features. As one way to overcome such limitations, various methods have been implemented to increase the resolution performance of photoresists and to eliminate interfering effects occurring in the semiconductor wafer manufacturing process.
In the fabrication of semiconductor devices multiple layers (levels) may be required for providing a multi-level interconnect structure. During the manufacture of integrated circuits it is common to place photoresist on top of a semiconductor wafer in desired patterns and to etch away or otherwise remove surrounding material not covered by the resist pattern in order to produce metal interconnect lines or other desired features. During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer. Such holes are commonly referred to as vias, i.e., when the hole extends through an insulating layer between two conductive areas. Metal interconnecting lines (trench lines) are typically formed over the vias to electrically interconnect the various semiconductor devices within and between multiple layers. The damascene process is a well known semiconductor fabrication method for forming electrical interconnects between layers by forming vias and trench lines.
For example, in the dual damascene process, a via is etched in an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over an underlying metal or conductive area. After a first photolithographic patterning step to define via openings a second photolithographic patterning step is carried out to define a trench line opening overlying and encompassing the via opening, the via openings and the trench openings then filled with metal (e.g., Al, Cu) to form an electrically conductive and contiguous dual damascene feature. The excess metal above the trench level is then typically removed and planarized by a chemical-mechanical polishing (CMP) processes to complete the manufacturing process of one level of a multi-level semiconductor device.
Frequently, the trench line photolithographic patterning step may fail due to a number of reasons including, for example, photomask misalignment, or an unsuccessful exposure and development process. As a result, the dual damascene feature may not be fully conductively contiguous leading to unacceptable electrical performance. To remedy these processing errors, the trench line photolithographic patterning step must be repeated requiring a reworking process to remove and reapply a photoresist layer for re-patterning including removing any residual photoresist or polymeric residue material remaining in the via opening. To remove the photoresist layer including residual photoresist or polymeric residue material, the prior art processes typically use at least one of a plasma dry etching process or a wet chemical stripping process.
One problem according to the prior art damascene reworking processes is that the via opening including the sidewalls and bottom portion may be damaged or leave residual photoresist or polymeric material thereby compromising the damascene feature to degrade performance including increasing resistivity.
There is therefore a need in the semiconductor processing art to develop a method for an improved damascene reworking process whereby damascene features including sidewall and bottom portions are protected from damage to improve damascene performance following reworking.
It is therefore an object of the invention to provide a method for an improved damascene reworking process whereby damascene features including sidewall and bottom portions are protected from damage to improve damascene performance following reworking while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for avoiding processing damage to an anisotropically etched damascene feature in a reworking process.
In a first embodiment, the method includes providing a substrate including a dielectric insulating layer including a first anisotropically etched opening formed in closed communication with an underlying conductive area the first anisotropically etched opening being at least partially filled with a plug of resinous polymeric material; providing a first photoresist layer over the first anisotropically etched opening the first photoresist layer photolithographically patterned for forming a second anisotropically etched opening overlying the first anisotropically etched opening; blanket depositing a flowable resinous polymeric material to form a resinous layer over the first photoresist layer in a reworking process to include filling a remaining portion of the first anisotropically etched opening; removing the resinous layer and the first photoresist layer in a planarizing process to reveal an upper surface of the substrate; and, depositing a second photoresist layer over the upper surface for photolithographic patterning of the second anisotropically etched opening overlying the first anisotropically etched opening in the reworking process.
These and other embodiments, aspects and features of the invention will become better understood from a detailed description of the preferred embodiments of the invention which are described below in conjunction with the accompanying drawings.